The present invention relates to testing of integrated circuits. In particular, the invention relates to testing of integrated circuits involving downloading test vectors via a high speed data interface.
The development of complex integrated circuits increasingly depends upon the ability to test the circuitry sufficiently to ensure proper operation. This is becoming increasingly difficult as the number of logic gates in a given integrated circuit increases. To test these logic gates, the number of input test data (referred to as xe2x80x9ctest vectorsxe2x80x9d) also must increase so that all possible input states, or at least a significant portion of them, are included in the test program. Traditionally, integrated circuits have been tested for functionality in the factory on a commercial test machine. Either the wafer is probed or the packaged part is tested. A sequence of test vectors is applied in parallel to the input pads or pins and comparisons with expected results are performed on the output pads or pins. The fault coverage is usually less than 100% and is dependent on how many test vectors there are, how well the test vectors were written, and the degree of complexity of the circuitry to be tested.
The problems with this prior-art testing scheme include the fact that commercial test sets (e.g., Automated Test Equipment) have difficulty working fast enough to test high speed parts. Also, the only way to test the packages once they have been soldered onto boards is to test them with a custom xe2x80x9cbed of nailsxe2x80x9d that disables other packaged chips on the board and applies test vectors to the package under test. This is becoming increasingly difficult as printed circuit boards with surface mount packages on both sides are becoming more common. Even further, it is not possible to test a package in the field or even in the factory when the printed circuit board on which it is embodied is plugged into its slot. For instance, in an application specific integrated circuit (ASIC) methodology, a core processor can be embedded in a design such that a vector set cannot be applied at the bond pads.
Many have advocated dealing with these test problems by adding Built In Self Test (BIST) circuitry on a chip. Here, a signal applied to the chip causes the BIST circuitry to perform a test. Typically, there is a pseudo-random sequence produced by a shift register with feedback. The sequence is applied to the circuitry under test and the outputs from the circuitry are compressed and compared with an expected signature. BIST has been used successfully in a number of chips. However, it too has drawbacks, including: while BIST solutions are known for regular structures such as memories, there is no general way known to produce BIST circuitry for arbitrary random logic with high fault coverage. In addition, BIST requires adding area overhead to the chip.
A recent development in integrated circuit testing is the use of the JTAG (Joint Test Action Group) test port for on site testing of an IC mounted on a board. This standard has been adopted by the Institute of Electrical and Electronics Engineers, Inc., as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, which is incorporated herein by reference. An overview of the development, definition, and application of this standard is provided in Test Access Port and Boundary-Scan Architecture, C. M. Maunder and R. E. Tulloss, published by the IEEE Computer Society Press, Los Alamitos, Calif. (1990).
FIG. 3 illustrates a block diagram of the components used in a typical JTAG testing scheme. As shown in FIG. 1, in a typical JTAG scheme, a Test Access Port (TAP) is added to each chip or grouping of chips on a board. The TAP includes three inputs: test clock (TCK), test mode select (TMS), and test data in (TDI). In addition, there is one output, test data output (TDO). TDI and TDO are daisy-chained from chip to chip, whereas TCK and TMS are broadcast to each chip in a group.
As shown in FIG. 3, every JTAG chip contains a boundary scan register 300, and a bypass register 301. The boundary scan register 300 serially shifts any desired data pattern from the TDI port into the input stages of the chip. The boundary scan register 300 receives input from the input terminals I1, . . . I3. It also receives system clock terminal CK1. All the inputs are received via TDI port. The boundary scan register generates the chip outputs over JI, . . . JI3 lines. All the outputs are shifted out of the chip via TDO port of the chip. Other lines not shown, are used to send signals in the other direction, (i.e., from the chip output circuitry to the chip output terminals.) Each chip also contains a TAP controller 302 that implements a standard state machine steered by the signal applied at the TMS terminal. In this regard, the TAP controller 302 selects one of sixteen states for shifting data and instructions into the registers, among other functions. The instruction register 303 allows test instructions to be entered into each chip, and the instruction decoder 304 serves to decode the instructions. The output of a given register is selected by multiplexers 307 and 308, and driven off-chip by the output buffer 309, which supplies the TDO signal. The external signals applied to the JTAG test access port are provided by a master controller, usually referred to as the xe2x80x9cJTAG masterxe2x80x9d.
The JTAG standard allows a chip to have arbitrary data serially scanned into its boundary scan register 300. This arbitrary data may be an input test vector or an output test result. The JTAG standard also supports tri-stating outputs. A standard scheme allows opens and shorts on the board or bond wires to be located. A chip can be tested by applying its entire factory vector set serially through the boundary scan register 300.
The JTAG standard also allows for optional registers to be added. For example, a manufacturer""s identification register 305 provides a unique code identifying the chip type. In addition, a user test register 306 may be defined, typically to provide support for triggering BIST and reading the test status results.
A problem with this JTAG testing scheme is that testing of the chip by serial scanning wherein one bit is serially scanned at a time is very slow, and time consuming.
FIGS. 4A and 4B illustrate another JTAG based testing scheme. A full description of this scheme may be found in U.S. Pat. No. 5,355,369 issued on Oct. 11, 1994 to Greenbergerl Alan J. et al., which is incorporated herein by reference.
In this scheme, most components are similar to FIG. 1, but two additional data registers, TDR 11 and JCON 10 are used to download the test vectors to the logic circuitry under test, and upload the results. Both TDR 11 and JCON 10 are compatible with the JTAG standard. TDR 11 is a serial shift register which is parallel readable and writeable by the digital processor core. JCON 10 is a serial scan register with parallel outputs on the chip. JCON 10 contains additional signals to provide flexibility in clocking the digital processor test program while it is in a board environment.
In this scheme, the board containing the digital processor normally provides a system clock to a clock terminal. If this clock is available and free running on the board, the JTAG may select it as the source of chip clock and begin testing. This allows the tests to be run at normal chip operational speed. The older JTAG schemes do not have JCON 10 and do not have flexibility to select a free running board clock, and the testing is very slow. The speed of this clock is dependent on system implementation.
This testing scheme has improved performance as it allows for testing the integrated circuit at full operational speed. But, the overall testing (including downloading of the test vectors) of the chip is very slow. Even though there are 16 bits in a cycle, only one bit of the test vectors is scanned and downloaded at a time. Thus, the downloading of test vectors into the chip takes a very long time, thereby slowing the whole testing process. Thus, many of the traditional methods of testing the digital processor involve downloading test programs serially through a slow test port into internal memory located on the digital processor device, and then resetting the digital processor device and executing the test programs starting from location zero inside the internal memory. The downloading is done serially which in turn increases the testing time and the cost of manufacturing the device.
Thus, there exists a need for an apparatus and a scheme for downloading test vectors at a higher speed thereby reducing the time for testing integrated circuits.
According to the principles of the present invention, a method and an apparatus for testing an integrated circuit by the use of a high speed data interface bus is provided. In the present invention, an integrated circuit having a programmable digital processor, a program (internal) memory, and a JTAG driver is coupled to an external memory via a high speed (parallel) interface bus. The external memory stores a plurality of test vectors to be used for testing operation of the integrated circuit, and the high speed interface bus is used to download these test vectors. The JTAG circuit is used to download the control program controlling the download of the test vectors.
In the inventive method, first, a control program (executable code) is downloaded through the JTAG port into an internal (program) memory. This control program then downloads the test vectors (which are stored in an external memory) into the internal memory at location 0x0 using the high speed data bus. Once the downloading is finished, the digital processor device resets and the test vectors start verifying the functionality of the digital processor and/or the peripheral circuits.
The proposed method and apparatus reduces the testing time by almost 50% because only a short program (control program) is downloaded via the slow serial port. The actual test programs are downloaded via a high speed interface bus, for example, a high speed external memory interface.